1. Field of the Invention
The present invention relates to a data encoding apparatus for encoding data for every data block of a predetermined number of pixels of data and a method of the same and to a camera system for compressing and encoding generated image data for every data block of the predetermined number of bits of data. More particularly, the present invention relates to a data encoding apparatus for JPEG encoding image data for every block of for example 8×8 pixels and a method of the same and to a camera system.
2. Description of the Related Art
In a natural image, adjoining pixel values frequently have correlation. When the spatial fluctuation (spatial frequency) of the pixel values when seen in a certain small region becomes small (low), and the image data in a real domain is transformed to data in a spatial frequency domain by a quadrature transform, the data tends to lean to the low frequency side. For this reason, when encoding the data in the spatial frequency domain, an average code length of the entire data can be. shortened by making the code length allocated to the data on the high frequency side shorter than that to the data on the low frequency side, so the amount of data can be compressed.
For example, in a discrete cosine transform (DCT) type encoding system of a standard international system for compressing and encoding still image data, that is, the color still image encoding system of the Joint Photographic Experts Group (JPEG), the input image data is divided into data blocks each consisting of 8×8 pixels, and each data block is subjected to one quadrature transform, DCT. By this, the 64 bits of image data of one data block are transformed to 64 DCT coefficients. These DCT coefficients are quantized by a quantization step determined for every coefficient, then one DC component and the other 63 AC components are encoded to Huffman codes by methods different from each other.
When the DCT coefficients are DC components, the data of the difference between continuous blocks are Huffman encoded. This is because the DC components between adjoining data blocks in a natural image have correlation in many cases, and the dispersion of differential values becomes smaller.
Also, when the DCT coefficients are AC components, the data string of the DCT coefficients rearranged to a sequence in accordance with the magnitude of the spatial frequency are encoded to a Huffman code in accordance with the combination of the value of non-zero coefficients and the number of the zero coefficients continuing before that. This is done to improve the compression efficiency by utilizing the property that quantized DCT transformed coefficients easily become zero at the high frequency side.
Note, there are two special cases in the encoding of AC components. One is a case where 16 or more AC components of zero coefficients continue in the above data string. In this case, one code referred to as a “zero run length” (ZRL) is generated for the 16 continuous zero coefficients. The other one is a case where the last AC component of the data string is the zero coefficient. In this case, only one code referred to as an “end of data block” (EOB) is generated for the zero coefficients continuing up to the last bit of the data string irrespective of the number thereof.
In both cases, one code is given to a plurality of zero coefficients together, so the compression efficiency is raised.
Here, a related art JPEG encoding apparatus will be concretely explained by referring to the drawings.
FIG. 10 is a schematic view of the configuration of a related art JPEG encoding apparatus. The JPEG encoding apparatus shown in FIG. 10 has a DCT/quantization unit 1, DCT buffer control unit 2, DCT buffer 3, and Huffman encoding unit 4.
The DCT/quantization unit 1 transforms image data D—IN input for every 8×8 pixel data block by DCT and quantizes 64 DCT coefficients obtained as a result of this by the quantization step determined for every coefficient. Then, an enable signal DCT—EN is changed to an active state and output of header data of a 8×8 pixel data block is notified, then 64 quantized DCT coefficients DCT—K are sequentially output to the DCT buffer control unit 2.
The DCT buffer control unit 2 sets the DCT buffer 3 in a write enable state by an enable signal W—EN when the enable signal DCT—EN of the DCT/quantization unit 1 changes to the active state, sequentially generates write addresses W—ADD of a zigzag (meander) scan sequence corresponding to the DCT coefficients DCT—K of the DCT/quantization unit 1, and sequentially writes the DCT coefficients DCT—K at these generated addresses.
Also, when an enable signal HUFF—EN of the Huffman encoding unit 4 changes to the active state, it sets the DCT buffer 3 in a read enable state by an enable signal R—EN, sequentially generates read addresses R—ADD and reads out DCT coefficients R—DATA from the DCT buffer 3, and sequentially outputs them to the Huffman encoding unit 4.
A more detailed explanation will be made of this DCT buffer control unit 2 with referring to FIG. 11.
FIG. 11 is a schematic view of the configuration for explaining this DCT buffer control unit 2. The DCT buffer control unit 2 shown in FIG. 11 has a latch circuit 21, zigzag (meander) address generation unit 22, and read address generation unit 23.
The latch circuit 21 is a circuit for holding the DCT coefficients DCT—K from the DCT/quantization unit 1 synchronous with a not illustrated clock signal and outputting them as write data W—DATA to the DCT buffer 2. The data W—DATA and the write address W—ADD are synchronously supplied to the DCT buffer 2 by this.
The zigzag address generation unit 22 monitors the state of the enable signal DCT—EN of the DCT/quantization unit 1, changes the write enable signal W—EN to the active state synchronous with detection of this active state, and sets the DCT buffer 3 in the write enable state. Further, it sequentially generates write addresses W—ADD in the zigzag scan sequence corresponding to the DCT coefficients DCT—K sequentially input from the. DCT/quantization unit 1 and sequentially writes the DCT coefficients W—DATA at these generated addresses. After writing 64 DCT coefficients into the DCT buffer 3, it returns the enable signal W—EN to a non-active state and returns to the monitoring state of the enable signal DCT—EN again.
The read address generation unit 23 monitors the state of the enable signal HUFF—EN of the Huffman encoding unit 4, changes the read enable signal R—EN to the active state synchronous with the detection of this active state, and sets the DCT buffer 3 in the read enable state. Further, it sequentially generates read addresses R—ADD, reads out the DCT coefficients from the DCT buffer 3, and sequentially outputs these read DCT coefficients R—DATA to the Huffman encoding unit 4.
FIGS. 12A and 12B are views of an example of a sequence of generating the DCT coefficients at the DCT/quantization unit 1 and the sequence of reading the DCT coefficients written in the DCT buffer 2 according to the sequence of the zigzag (meander) scan.
In FIG. 12A, the numerals corresponding to the DCT coefficients of the data blocks expressed by two dimensions of 8×8 indicate the sequence of the generation of the DCT coefficients. The spatial frequency of these DCT coefficients becomes higher from the left to right and from the upper stage to lower stage. Also, the arrows indicated by the dotted lines in this illustration show the sequence of the zigzag scan. The write addresses W—ADD are generated at the zigzag scan address generation unit 22 so that the data is read from the DCT buffer 2 in accordance with this sequence.
As seen from this illustration, the sequence of the zigzag scan is set so that the spatial frequencies in a horizontal direction and a vertical direction equally become higher in accordance with this sequence.
Also, the numerals of the DCT coefficients in FIG. 12B correspond to the numerals in FIG. 12A. The arrows indicated by the dotted lines indicate the sequence of the reading of the DCT coefficients written in the DCT buffer 2. The DCT coefficients are sequentially read from the DCT buffer 2 in the sequence from left to right and from the upper stage to lower stage of the data blocks expressed by the two dimensions shown in the figure. Also, this data block indicates an address space of the DCT buffer 2. The address value becomes larger from for example the left to right and from the upper stage to the lower stage. Accordingly, in the read address generation unit 23, it is not necessary to generate a complex address as in the zigzag scan address generation unit 22. Addresses simply increasing by predetermined steps from for example the first to 64-th DCT coefficients are generated.
The above explanation was made for the DCT buffer control unit 2 of FIG. 10.
The DCT buffer 3 of FIG. 10 stores the DCT coefficients W—DATA sequentially generated in the DCT/quantization unit 1 in storage areas designated by the write addresses W—ADD when set in the write enable state by the enable signal W—EN from the DCT buffer control unit 2.
Also, when set in the read enable state by the enable signal R—EN from the DCT buffer control unit 2, the DCT buffer 3 reads the DCT coefficients R—DATA from the storage area designated by the read address R—ADD and outputs this to the Huffman encoding unit 4.
The Huffman encoding unit 4 sets the enable signal HUFF—EN in the active state when performing the encoding, Huffman encodes the DCT coefficients sequentially read from the DCT buffer 3 by the DCT buffer control unit 2, and outputs a Huffman code H—CODE. Also, when a signal S—EOB for indicating an end of encoding of the data block is input from the EOB detection unit 5, it outputs the code EOB.
This Huffman encoding unit 4 will be explained in further detail with referring to FIG. 13.
FIG. 13 is a schematic view of the configuration for explaining this Huffman encoding unit 4. The Huffman encoding unit 4 shown in FIG. 13 has a zero data counter 41, Huffman code table address generation unit 42, Huffman code table 43, ZRL judgment unit 44, and data control unit 45.
The zero data counter 41 is a counter for counting the number of continuous zero coefficients of the AC components in the data string of the DCT coefficients R—DATA read from the DCT buffer 3. It initializes this count to zero at a point of time when the encoding of one block is started and increments the count by one whenever zero coefficients of AC components are input to the DCT coefficients R—DATA. Then, when the non-zero coefficients are input to the DCT coefficients R—DATA, it outputs the non-zero coefficients DATA and a count Z—CT to the Huffman code table address generation unit 42 and the ZRL judgment unit 44 and initializes the count to zero after that. Also, when a signal S—ZRL for notifying the generation of the code ZRL is input, it decrements a value “16” from this count of zero coefficients.
The Huffman code table address generation unit 42 generates an address TBL—ADD of the Huffman code table 43 in accordance with the combination of the non-zero coefficients DATA and the count Z—CT output from the zero data counter 41 and outputs them to the Huffman code table 43.
Also, it generates the address TBL—ADD corresponding to the code ZRL when a signal S—ZRL indicating the generation of the code ZRL is input, while generates the address TBL—ADD of the Huffman code table 43 corresponding to the code EOB when a signal S—EOB indicating the end of encoding of the data block is input.
The Huffman code table 43 extracts the Huffman code corresponding to the table address TBL—ADD from a predetermined data table and outputs this.
The ZRL judgment unit 44 generates the signal S—ZRL indicating the generation of the code ZRL when the count of the zero coefficients is “16” or more and then the non-zero coefficients are input and outputs them to the zero data counter 41, the Huffman code table address generation unit 42, and the data control unit 45.
The data control unit 45 sets the enable signal HUFF—EN in the active state upon receipt of an activation signal STA and starts reading the DCT coefficients from the DCT buffer 3.
Also, when the signal S—ZRL for indicating the generation of the code ZRL is input from the ZRL judgment unit 44, it temporarily sets the enable signal HUFF—EN in the non-active state, suspends the reading of the DCT coefficients from the DCT buffer 3, and returns the enable signal HUFF—EN to the active state again after the generation of the code ZRL to re-start the encoding.
When the reading of one data block's worth of the DCT coefficients is terminated or when the signal S—EOB for indicating the end of the encoding of the data block is input, it returns the enable signal HUFF—EN to the non-active state and terminates the Huffman encoding.
The above explanation was made for the Huffman encoding unit 4 of FIG. 10.
The EOB judgment unit 5 of FIG. 10 detects whether or not the value of the DCT coefficients read out at the end of one data block are zero based on the DCT coefficients R—DATA read from the DCT buffer 3 and the address R—ADD thereof. When this value is zero, it generates a signal S—EOB indicating the end of encoding of the data block and outputs this to the Huffman encoding unit 4.
Next, an explanation will be made of the operation of the JPEG encoding apparatus of FIG. 10 having the above configuration.
FIGS. 14A to 14F show timing charts for explaining an operation for rearrangement of the DCT coefficients in the JPEG encoding apparatus shown in FIG. 10 to a zigzag scan sequence. Among them, FIG. 14A to FIG. 14F show timing charts of the operation when the DCT coefficients are written into the DCT buffer 3, while the remaining FIG. 14G to FIG. 14K show timing charts of an operation when the DCT coefficients are read from the DCT buffer 3.
When the enable signal DCT EN (FIG. 14B) of the DCT/quantization unit 1 is set in the active state synchronous to the clock signal (FIG. 14A), the write enable signal W—EN (FIG. 14D) is set in the active state in the zigzag address generation unit 22 detecting this active state and, at the same time, the write address W—ADD (FIG. 14E) is generated according to the zigzag sequence. Also, the DCT coefficients W—DATA (FIG. 14F) obtained by latching of the DCT coefficients DCT—K (FIG. 14C) of the DCT/quantization unit 1 at the latch circuit 21 and the output of the write address W—ADD generated at the zigzag address generation unit 22 are output to the DCT buffer 3 synchronous with the clock signal. The write enable signal W—EN is returned to the non-active state again after 64 DCT coefficients are written into the DCT buffer 3.
When the enable signal HUFF—EN (FIG. 14H) of the Huffman encoding unit 4 is set in the active state synchronous with the clock signal (FIG. 14G), the enable signal R—EN (FIG. 14I) is set in the active state in the read address generation unit 23 detecting this active state and the read addresses R—ADD (FIG. 14J) are sequentially generated. By this, the DCT coefficients R—DATA (FIG. 14K) stored in the DCT buffer 3 are sequentially read and input to the Huffman encoding unit 4. The read enable signal R—EN is returned to the non-active state again after 64 DCT coefficients are read from the DCT buffer 3.
FIG. 15 is a view of an example of the DCT coefficients of 8×8 pixel data block read from the DCT buffer 3 and input to the Huffman encoding unit 4, while FIGS. 16A to 16G are timing charts for explaining the operation of the Huffman encoding unit 4 when the DCT coefficients shown in FIG. 15 are input. An explanation will be made of operations at the time T1 to time T8 in this timing chart.
Time T1: The read enable signal R—EN (FIG. 16B) changes to the active state synchronous with the clock signal (FIG. 16A), then the DCT coefficients R—DATA (FIG. 16C) are input to the Huffman encoding unit 4. The DCT coefficients R—DATA input to the start of the data block are DC components. The processing is different from that for the AC components subsequently input. For the DC components, the addresses TBL—ADD of the Huffman code table for the DC components are generated based on the differential value relative to the previously input DC components of the 8×8 pixel data block. A Huffman code H—CODE in accordance with this is output from the Huffman code table 43.
Time T2: Non-zero data (value “2”) are input as the DCT coefficients R—DATA. An addresses TBL—ADD (FIG. 16G) in accordance with the combination of the value “2” and a value “1” of the count Z—CT (FIG. 16D) of the zero coefficients continuously input before the value “2” are generated at the Huffman code table address generation unit 42. The Huffman code H—CODE in accordance with this is output from the Huffman code table 43.
Time T3: The non-zero data (value “1”) are input as the DCT coefficients R—DATA. An address TBL—ADD in accordance with the combination of this value “1” and a value “0” of the count Z—CT of the zero coefficients continuously input before this value “1” are generated. The Huffman code H—CDE in accordance with this is output.
Time T4: The count Z—CT of the continuously input zero coefficients reaches the value “16”, but in this stage, it cannot be decided which of the code ZRL or the code EOB is to be generated, so the encoding is not carried out. Namely, there are two such cases: a case where zeros appear up to the last DCT coefficient and one code EOB is generated and a case where one or more codes ZRL are generated by non-zero DCT coefficients present before the last DCT coefficient. It cannot be decided at the time T4 which case is exhibited, so the address TBL ADD is not generated.
Time T5: Non-zero data (value “1”) is input as the DCT coefficient R—DATA. Also, at this time, the count Z—CT of the continuously input zero coefficients is a value more than 16, i.e., “39”, so the signal S—ZRL (FIG. 16E) for indicating the generation of the code ZRL is generated at the ZRL judgment unit 44. Due to this, an address TBL—ADD corresponding to the code ZRL is input to the Huffman code table 43 and the code ZRL is output, while the value “16” is subtracted from the count Z—CT of the zero coefficients. Further, the enable signal HUFF—EN is set in the non-active state, whereupon the reading of the DCT coefficients from the DCT buffer 3 is temporarily suspended.
Time T6: Since the reading of the DCT coefficients is suspended, the DCT coefficients R—DATA keep the non-zero data (value “1”) the same as that at the time T5 as it is, and the count Z—CT of the zero coefficients is a value “23”, so the signal S—ZRL for indicating the generation of the code ZRL is continuously generated. Due to this, the address TBL—ADD corresponding to the code ZRL is input to the Huffman code table 43 and the code ZRL is output, while the value “16” is further subtracted from the count Z—CT of the zero coefficients. Also, the enable signal HUFF—EN is in the non-active state as it is, so the reading of the DCT coefficients from the DCT buffer 3 is continuously suspended.
Time T7: Since the reading of the DCT coefficients is suspended, the DCT coefficients R—DATA are non-zero (value “1”) data the same as that at the time T6, but the count Z—CT of the zero coefficients becomes a value “7” and becomes smaller than the value “16”, so the code ZRL is not generated. In place of this, an addresses TBL—ADD in accordance with the combination of the value “1” of the DCT coefficients R—DATA and the value “7” of the count Z—CT of the zero coefficients are generated. A Huffman code H—CODE in accordance with this is generated.
Time T8: Since the value of the last DCT coefficient becomes zero, the signal S—EOB indicating the end of encoding of the data block is output from the EOB judgment unit 5. An address TBL—ADD corresponding to the code EOB is generated at the Huffman code table address generation unit 42 receiving this and input to the Huffman code table unit 43. Also, the enable signal HUFF—EN is returned to the non-active state at the data control unit 45, and the enable signal R—EN is returned to the non-active state at the read address generation unit 23 in accordance with this, so the read operation of the data from the DCT buffer 3 is terminated.
In this way, in the related art JPEG encoding apparatus, even if all AC components are zero, a possibility of the code ZRL remains until it is confirmed that the value of the last data of the zigzag scan is zero, so the code EOB cannot be generated. Namely, even in a case where only the code EOB is generated as a result, all of one data block's worth of 64 DCT coefficients must be confirmed, so there is the disadvantage in that the processing time relating to the encoding cannot be shortened.
Also, when 16 or more DCT coefficients continuously become zero, one code of the code ZRL or code EOB should be generated, but it cannot be decided which code is to be generated until the non-zero DCT coefficients are input or zeros continue up to the end, so the code ZRL is not generated. For this reason, when the non-zero DCT coefficients are input, it is necessary to once suspend the input of the DCT coefficients from the DCT buffer 3 and generate the code ZRL. Namely, there is the disadvantage in that a delay time is generated in the reading of the DCT coefficients whenever the code ZRL is generated.